Design Verification Engineer Resume

Desired Industry: Computer Hardware	SpiderID: 839
Desired Job Location: Phoenix, Arizona	Date Posted: 6/26/2004
Type of Position: Full-Time Permanent	Availability Date: Immediate
Desired Wage:
	U.S. Work Authorization: Other
Job Level: New Grad/Entry Level	Willing to Travel: Yes, More Than 75%
Highest Degree Attained: Masters	Willing to Relocate: Yes

Objective:
Seeking a fulltime/intern/Co-op position that offers challenging opportunities in ASIC Design / Design Verification.

Experience:
ECE Department, The University of Arizona, Tucson, AZ. (Aug ’03 to Dec ’03)
Research Assistant, Internet Technology Lab (ITL)
Built a wireless sensor network as part of a building architecture project with off the shelf components using PIC microcontrollers and 5 transceiver boards (nodes). Each node has 3 different sensors (light, temperature, relative humidity).

iReady Corporation, Santa Clara, CA. (June ’03 to Aug ‘03)
Design Verification Intern, Design Verification Group
Responsibilities:
* Converted and debugged around 1000 assertions for the DUT from a proprietary assertion language (Verix) to the latest industry standard assertion language PSL 1.1.
* Ported the company’s existing perl environment for verilog simulation to the Dynamic Assertion Based Verification platform of Cadence NCverilog.
* Created a generic PSL assertion library module for most common assertions. The modules can be instantiated in-line with the design.

ECE Department, The University of Arizona, Tucson, AZ. (Jan ’02 to May ’03)
Teaching Assistant, Computer Architecture (ECE 369)
Responsibilities:
* Setup a Verilog HDL lab as part of the course work. The lab uses Altera MAX Plus and Quartus II software for simulation and synthesis.
* The lab includes simple digital logic design using Verilog HDL to MIPS 32-bit ALU Implementation, MIPS single cycle data path and control logic, multicycle data path design and pipelined data path design using Verilog HDL.
* The final project includes the Hazard Detection Unit and the Forwarding Unit and executes most of the MIPS instruction set.

C-Logic India, Coimbatore, India. (June ‘00 to June ’01)
ASIC Verification Engineer, Design Verification Group
Projects:
* Verification of ASIC Interface Chip between Fiber Channel (FC) and Gigabit Ethernet
Environment Setup: Two FC to Gbe chip cores were connected back-to-back through the Gbe interface. The verification environment generated FC Frames and fed to one of the chips (core) on the FC interface side. The received FC frames on the other chip were checked and verified for proper conversion and communication through the Gbe channel. TOOLS: Cadence NCverilog, Viewlogic.

* Synthesizeable controller for SRAM (K6T4016c3B)
The controller was developed as part of a microcontroller design that used the Samsung SRAM chips as memory. The pre and post synthesis simulation successfully met the design requirement for speed (20 MHz). TOOLS: Finsim, Viewlogic, Mentor graphics Leonardo Spectrum.

C-Logic India, Coimbatore, India. (Aug ‘99 to March ’00)
Co – Op Engineer.
* Universal Serial Bus – Serial Interface Engine (SIE)
A Serial Interface Engine (SIE) is designed and simulated following the USB1.1 specification. The project included a DPLL, USB protocol-handling component, CRC checking module and a FIFO. This design was awarded the best senior project.

Education:
MS, Electrical & Computer Engineering 2001-2003
The University of Arizona.
GPA: 3.0/4.0
BE, Electronics & Communication Engineering 1996 - 2000
Bharathiyar University.
GPA: 3.94/4.0

Skills:
PROGRAMMING : Verilog, C,C++, Perl, PSL 1.1(Property Specification Language),
System Verilog Assertion, OVL (Open Verification Library).
CAD TOOLS : Cadence NC Verilog, Cadence Testbuilder, Viewlogic, DAI
Signal Scan, Finsim, Altera MAX Plus, Quartus II, Novas Debussy,
SimVision, Spice, Pspice.
SYNTHESIS TOOLS : Mentor Graphics Leonardo Spectrum, Synplicity Synplify.
LAYOUT TOOL : MAGIC.
OPERATING SYSTEMS : UNIX, SUN SOLARIS, Windows 9x/NT/2000, LINUX.

Candidate Contact Information:

Name: Mahesh Indran
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