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Electrical engineer ifull time Resume
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| Desired Industry: Computer Hardware |
SpiderID: 6358 |
| Desired Job Location: dallas, Texas |
Date Posted: 4/3/2006 |
| Type of Position: Full-Time Temporary |
Availability Date: May 2007 |
| Desired Wage: $70000 |
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U.S. Work Authorization: Yes |
| Job Level: New Grad/Entry Level |
Willing to Travel: Yes, Less Than 25% |
| Highest Degree Attained: Masters |
Willing to Relocate: Yes |
Objective:
To obtain a full time position in the field of electrical engineering.
Experience:
Academic Experience
• Designed and implemented a 25- bit Sequence Detector (Verilog/Synopsys, UTD, Aug 2006).Built it as a Finite State machine using behavioral description. 106 cells reported after synthesis.
• Designed and implemented an Inverter (Cadence, UTD, Sep 2006) with equal rise and fall times(delay difference < 5ps) and minimal energy delay product.
• Designed a negative edge triggered D Flip Flop (Cadence, UTD, Oct 2006) with asynchronous reset with minimum diffusion break and minimum possible cell height. Analyzed the Worst case Setup and Hold timings of the D Flip Flop using Awaves.
• Created a Standard library of cells (Cadence/130nm, UTD, Oct 2006) consisting of nand2, nand3, nand4, nor2, nor3, xor2, xnor2, aoi12, aoi22, oai12, oai22, inverter, D flip-flop. Functionality of each cell verified using Awaves and HSPICE
• Layout and Verification of the 25-bit Sequence Detector (Cadence/Encounter, UTD, Nov 2006): Automatic placement and routing was performed for the design. The functionality of the design was verified using Awaves and HSPICE.
• Designed and implemented a Built in Self Test (BIST) System (Verilog/Synopsys, UTD, March 2006). Integrated a Pseudo Random Pattern Generator, given Ciruit under Test and Multiple Input Signature Register to make the system built in self-testable.
• Generated a test vector for a stuck at fault in the given combinational circuit using D- Algorithm and testablilty measures such as controllability and observability. The generated test vector from this analysis was fed as an external vector in Tetramax and the faults detected were compared.
• Performed fault collapsing (Verilog/Synopsys, UTD, February 2007) for a given combinational circuit. Demonstrated parallel, concurrent, deductive and critical path tracing fault simulation for the given test vector. Synthesized the circuit and found all faults detected by the vector using Tetramax.
• Designed and implemented an event driven (asynchronous) circuit for Railway Crossing System (Verilog/Synopsys/Scirocco, UTD, February 2006) used to control the gates and a red flashing light at a railway level crossing. The stuck-at-faults, test vectors and fault coverage were reported in Tetramax
• Implemented L3 Inclusive and victim cache based Exclusive cache (Simplescalar, UTD, Nov 2005) in C. The performance tradeoffs between the two configurations in miss rate, Instruction per Cycle, power and area for various benchmarks was compared.
• Designed a 16-bit Carry Look Ahead (CLA) Adder (Verilog/Synopsys, UTD, April 2006) based on CLA-4 units. Analyzed the synthesized circuit for worst case delay examples and found the delay from the timing report generated
INDUSTRY EXPERIENCE
• Intern, Bharath Electronics, Bangalore, India, Feb 2004-May 2004: Provided assistance and technical support in the Switching Department. Verified and tested various modules using MAX+PLUS II (Wrote testbenches in VHDL)
• HR Assistant, Asian Catalyst and Chemicals, Bangalore, India, Jan 2005-May 2005: Led product promotion, handled customer calls and bank transactions.
• Engineer Trainee, Sify limited, Mumbai, India, Jul 2004-Oct 2004: Handled customer calls, performed data entry, installed and maintained servers in an internet data center as a team member of the Operations Team.
Education:
Master of Science, Electrical Engineering
University of Texas at Dallas
(May 2007) Current GPA: 3.44
Bachelor of Engineering, Electronics and Communication Engineering
M.S.Ramaiah Institute of Technology, India
(June 2004) Aggregate: 77%
Skills:
ENGINEERING SKILLS/ABILITIES
• HDLs: VHDL, Verilog.
• Tools: Synopsys (Design Compiler, Design Analyzer, Scirocco and Tetramax) and Cadence (Virtuoso, Encounter), Spectre, Pathmill, Altera Quartus II, ModelSim, HSPICE, Awaves, Code Composer Studio (DSP), Simplescalar
• Documenting Tools: Microsoft Office
• Operating Systems: Linux, Solaris, Windows.
• Abilities: CMOS Circuit Design, Layout, Functional Verification, VLSI Testing, Computer Architecture, DRC, LVS
• Software Languages and Assembly: C and C++, MIPS, 16F84, DLX, ARM, Intel-8085, 8086 and 8051.
Additional Information:
ACTIVITIES
• Organized and participated in dance shows at Shiamak Davar Institute of Performing Arts (SDIPA)
• Runner up at the University Idol at University of Texas at Dallas organized by Indian Student Association. Also took active part in the Indian Cultural meet. Performed in various stage shows like musical skits and fashion show.
• Participated in one of the best TV quiz shows in India. Also won a prize in a quiz competition conducted at the state level.
• Regularly practice yoga and meditation.
Reference:
Available upon request
Candidate Contact Information:
This candidate has chosen not to make contact information available on this page.
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