Engineering Resume

Desired Industry: Engineering	SpiderID: 28793
Desired Job Location: Colorado Springs, Colorado	Date Posted: 9/22/2009
Type of Position: Full-Time Permanent	Availability Date: 09/18/2009
Desired Wage: 100000
	U.S. Work Authorization: Yes
Job Level: Management (Manager, Director)	Willing to Travel: Yes, 25-50%
Highest Degree Attained: Bachelors	Willing to Relocate: Yes

Objective:
Electrical engineer experienced in all facets of the design process from idea conception, specification and architecture development, design, evaluation and debug, qualification and test. Strong organizational, leadership and strategic skills for bringing projects to successful completion. Proven track record of delivering programs with cutting edge technology on time with aggressive schedules and difficult specifications. Excellent problem solving skills, constantly driving ways to improve methods and quality assurance for high yielding products.

Experience:
MARVELL SEMICONDUCTOR INC., Colorado Springs, CO 2006 - 2009
A leading fabless semiconductor company

Program and Analog Design Engineering Manager
Lead development of mixed signal Intellectual Property (IP) for Marvell Cellular System on a Chip (SOC) wireless products in 65nm and 40nm technology, and the migration of 180nm, 130nm and 90nm circuits to a new foundry. Direct management and development of 12 analog designers.
• Lead porting of Intel 180nm designs to a low cost foundry in less than 4 months. Worked directly with Marvell Operations and TSMC foundry teams to tune process to meet specific device characteristics minimizing redesign of over 40 analog and IO circuits which resulted in a 80% cost reduction.
• Migrated 15 Intel 90nm mixed-signal designs to TSMC 65nm process in 5 weeks and taped out the 1st Marvell 65nm testchip. The results were highly recognized as a major success due to the quick execution times and the cost savings achieved. Marvell received the “2009 Award of Excellence” from RIM for the quality of the products which incorporated these circuits.
• Developed and taped out the 1st 45nm and 40nm designs for Marvel on aggressive schedules. These efforts included establishing and bore cleaning the design environment and tools, evaluating and proving out the process models and devices, defining circuit specifications, circuit design, simulation, layout, and evaluation of 15 mixed signal designs.
• Drove several improvements for the design environment and verification measures of IP collateral prior to delivery to increase quality and reduce integration efforts as the SOC level. This shaved 20% off our design schedule.

INTEL CORPORATION, Colorado Springs, CO 2000 – 2006
Mixed Signal Design Manager (2001 – 2006)
Managed 15 analog design engineers. Technically managed the execution of mixed signal Intellectual Property (IP) for 90nm low power technology and started initial circuit migration and test chip development in Intel 65nm process.
• Led design team and managed programs working directly with the designers and customers on specification development, circuit design, evaluation, debug and redesign of SOC analog circuits, including on-chip regulators, Temp sensors, A/D, oscillators, PLLs, I/O, DDR, reset circuits, USB and Touch Screen Interface in 90nm low power technology. These designs work successfully, and are in production on 7 products.
• Worked with Intel 90nm process engineers to enhance the devices and models for power and analog performance.
• Developed and released first Intel 65nm mixed signal test chip on aggressive timeline which resulted in a 30% power reduction.

Senior IC Design Engineer (2000)
Design of low power circuits for wireless communication IC’s.
• Designed clock divider circuits for a PLL, a low impedance switch and ported standard cells for use in analog circuits.
• Worked with Intel ESD (Electrostatic Discharge) team on circuits for mobile products.
• Represented Intel on the ESDA (Electrostatic Discharge Association) committees developing standards for the semiconductor industry.

FORD MICROELECTRONICS, INC, Colorado Springs, CO (1993 – 2000)
Senior IC Design Engineer (1999 - 2000)
Design of ESD circuits for FMI products. Experienced in all phases of CMOS IC design including interactive conceptual work with the customer, logic and circuit design, simulation, behavioral modeling, timing files, layout supervision and bench evaluation.
• Represented Ford (Visteon) on the ESDA standards committees developing standards for the electronics industry.

Senior Reliability Physics & Failure Analysis (FA) Engineer (1993 - 1999)
Managed reliability and failure analysis concerns for FMI custom ASIC mixed-signal designs.
• Team leader directed the activities of eight engineers and technicians to support the design, evaluation and qualification of 8 FMI ASIC designs. Investigated concerns relating to design, layout, process and packaging, and performed various electrical, mechanical, environmental stresses, and failure analyses. Ensured products met production qualification requirements.
• Conducted reliability evaluations on 17 products including circuit board design, test vector development, environment, electrical and mechanical stressing, and testing of IC's. Exposed defects and applied corrective measures.
• Performed FA services on over 25 custom IC's and field returns for qualification and production line shut downs. This included de-capping, de-processing, cross sectioning, SEM operation, X-ray, Emission microscopy, Acoustic Microscopy, liquid crystal analysis, micro probing and laser surgery.
• Represented Ford (Visteon) at JEDEC, AEC (Automotive Electronics Council) and the ESDA to align Ford, GM and Chrysler automotive reliability specifications. Other areas of expertise were in ESD design and EMC.

GTE GOVERMENT SYSTEMS & LORAL COMMAND & CONTROL SYSTEMS, 1992 – 1993
Military & Government civilian contractor
Worked at both GTE Government Systems and Loral Command & Control Systems as a Systems Network Engineer, Support Engineer and Test Engineer.
• Top Secret Clearance.
• Performed analysis, integration, and interoperability of multiple communications systems, maintenance of circuit and system Database management system, prepared and presented briefings on C3 Systems.
• Provided Electrical/Mechanical design for Space Operations Center, and testing software and hardware for the development of a US Army networking system.

UNITED STATES ARMY, Colorado Springs, CO 1983 – 1997
Sergeant First Class (E-7)
Served in both the United States Army (1983 - 1987) and United States Army Reserve (1987 - 1997) in Infantry, Air Defense Artillery and the US Army schools.

Education:
BSEE, University of Colorado - Colorado Springs, CO
Graduate level courses focusing on microelectronics, University of Colorado - Colorado Springs, CO

Affiliations:
IEEE, ESDA,

Skills:
Reliability physics, electrical engineer, failure analysis, design engineering, microsoft office, microsoft project, excel, word, UNIX, CAD, layout, leadership, project management, program management, supervisor, team lead, scheduling, budgeting, problem solving, decisive

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