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| Desired Industry: Computer Hardware |
SpiderID: 26307 |
| Desired Job Location: Silicon Valley, California |
Date Posted: 4/26/2009 |
| Type of Position: Full-Time Permanent |
Availability Date: Immidiate |
| Desired Wage: |
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U.S. Work Authorization: Yes |
| Job Level: Experienced with over 2 years experience |
Willing to Travel: Yes, 50-75% |
| Highest Degree Attained: Masters |
Willing to Relocate: Yes |
Objective:
Experienced HW Engineer with complete product lifecycle experience- Micro-architecture Development, Transistor-level Custom Circuit Design, CAD flows, Pre-Silicon Verification, to delivering final design for volume production.
Looking for challenging opportunities that utilize my technical skills as well as my inter-personal and communication skills.
Experience:
PROFESSIONAL EXPERIENCE
SUN Microsystems, Santa Clara, CA 2005 Present
SRAM Circuit Design Engineer, Flagship Next Generation CMT Micro-processor (Niagara products)
16 core, multi-threaded, 45nm processor with on-chip Ethernet feature.
Designed and implemented a 1Read 1Write custom Dual-Port SRAM Register File block and 12 Compiled Memory Dual-Port Register File SRAM blocks.
Ensured on-time completion, with all design margins met with a 10% margin, and power, IR drop constraints met.
Demonstrated good understanding of RTL, performed schematic entry, layout supervision, SPICE simulations of the Critical Path for verifying timing budget and measuring design margins.
Ensured design robustness by running CAD tools for Power measurement, Noise analysis, Clock propagation, Electro-migration and IR drop analysis and static timing analysis.
Ensured Logical Equivalence between SRAM circuit designs and RTL using Innologic devised test-benches to verify RTL vs Schematic equivalence.
Lead for pre-layout abstract generation and database release for all SRAM blocks Interfaced with Integration team and CAD team to identify and solve problems and provided quick solutions.
Developed Electrical Rule Checker tool along with CAD team to ensure critical circuit design criteria such as beta ratio, leakage, writability, dynamic circuit checks, etc were met as per spec.
Devised automation scripts in perl for running back-end flows to ensure speedy and accurate results.
Custom Circuit Design, SRAM, T1000 microprocessor
8 core, multi-threaded, 65 nm processor with on-chip Ethernet and PCIexpress features
Performed clock flow analysis on 15 SRAM blocks for test chip, helped to identify faulty clock header circuits and make suitable fixes
Developed GUI based tool MarginSim to automate spice simulations for calculating design margins for SRAM blocks and tabulated results. It incorporated the spice models at various process corners and the criteria for measuring margins.
Owned CAD tool for measuring noise violations on SRAM blocks, identified circuits that were not meeting the design criteria limits and worked with the design owners to fix them.
Cluster level Electro-migration/ IR drop analysis at the Cluster level, Victoria Falls microprocessor
Analyzed the Electro-migration and IR drop on 5 clusters using SUN Internal CAD tools.
Identified areas on the chip that could potentially be a problem and worked with the SRAM block owners and layout designers to make fixes in order to ensure the design reliability.
Logic Verification, Flagship Next Generation CMT Microprocessor, Niagara family
Designed and implemented interface connection checkers between SERDES and Network Interface Unit, Link Framing Unit and the Memory Controller Unit. 2 Critical RTL bugs were caught pre-tape out within a week of deployment.
Prepared a test plan to measure the clock gating efficiency in cluster headers.
Calculated the power savings efficiency by measuring the flop activity using C code and perl scripts.
Graduate Student Intern, SUN Microsystems, Feb 2005 Aug 2005
Conducted Substrate Modeling simulations to demonstrate the switching effects of large aggressor transistors on SRAM bit cell stability.
Simulated Delay Chain Circuits and conducted Monte-Carlo simulations using a SUN Internal CAD tools.
Performed a Comparative Analysis of the difference in delay values at various process corners, and between devices of different channel lengths
Assisted SRAM block owners with running back-end CAD tool, gained experience to design trade-offs.
Device Fabrication, Stanford Nanofabrication Facility, Aug 2004 Sept 2005
Fabricated micro-channels, micro-reservoirs, micro-grippers and comb-drive actuators using the photolithography, Deep Reactive Ion Etching and Critical Point Dryer steps on SOI wafers
Conducted wafer-bonding experiments using Benzocyclobutene, organic polymer glue, to obtain a stack of silicon wafers.
Designed experiments to form interconnections between two wafer layers without affecting the bond strength
Engineer Trainee, Indian Space Research Organization (ISRO), July 2000 July 2001
Implemented PC-Add on Frame synchronizer, an EPLD based circuit board that acquires serial RF signals coming in from satellites and makes them PC compatible.
Design of the board layout and programming EPLDs, validation testing by incorporating it in a PC using the ISA bus.
Verification of the error tolerance limits of incoming data with a standard stored pattern for further computations to ensure that it was within the threshold allowed.
Education:
M.S. Electrical Engineering, The University of Texas at Arlington, 2005
B.S. Electronics & Communication Engineering, Bangalore University, India, 2001
University of Santa Cruz, Extension
Digital Design Using System Verilog
Stanford Center for Professional Development
EE313 - Digital MOS Integrated Circuits 07
EE287 - Introduction to VLSI Systems 06
Affiliations:
IEEE
Skills:
TECHNICAL SKILLS
EDA tools: Cadence tools for Schematic entry and layout, Virtuoso, Starsim, SPICE, Pathmill, DRC,LVS,
Extraction tools, Debussy/Verdi, VCS
Languages: Verilog, PERL, C, C++
Platforms: UNIX, LINUX, SUN Solaris CDE and Windows
Lab Equipment: C-V meters, Oscilloscopes, Logic analyzers, Signal generators, Power meters
Additional Information:
COMMUNITY INVOLVEMENT
Served as a mentor for high school students in East Palo Alto with BUILD
Participated in charity fund raising events Avon Walk, March Of Dimes
Candidate Contact Information:
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