Hardware Design/Validation Engineer Resume

Desired Industry: Computer Hardware	SpiderID: 18297
Desired Job Location: San Jose, California	Date Posted: 1/10/2008
Type of Position: Full-Time Permanent	Availability Date: 1/10/08
Desired Wage:
	U.S. Work Authorization: Yes
Job Level: New Grad/Entry Level	Willing to Travel:
Highest Degree Attained: Masters	Willing to Relocate: Yes

Objective:
Seeking a full time Position as a Hardware Design/Validation Engineer

Experience:
ASIC Design Engineer Trainee, (Pelican Networks Jan ’07 – Aug’07)
Worked as an Intern for Physical Design Team (PD) for 0.13um ASIC
• Responsible for weekly ASIC implementation snaps. Work included RTL linting, DFT insertion, block synthesis, timing checks and LEC, full chip integration
• Analyzed RTL design logic cone changes and implemented GATE ECO to P&R netlist by writing TCL scripts. Verification included logic equivalency checks, scan integrity checks, open pins checks
• Familiar with scripts used to synthesize design using Cadence RTL Compiler.
• Worked with Synopsys PrimeTime static timing analysis used in block and full chip timing closure. Assisted with writing Perl scripts to parse timing reports
• Debugged SDF back annotated delay based full chip gate level simulations by understanding the SRAM Memory Models

Ethernet Packet Generator block for FPGA design
• Designed and implemented Verilog RTL for the packet generator
• Simulated the design using Verilog Test bench

Student Asst. - Undergrad Admissions (San Jose State U. May ’06 – Dec ’06)
Assisted with verifying student applications for the Undergraduate admissions
Assisted with phone support for San Jose State enrollment services
Assisted with maintaining student records, scanning documents and such

Instructional Student Asst. (San Jose State Univ. Fall ’05)
Administered the lab for MS-Access. Assisted lab students and graded their
assignments

Education:
Master of Science in Electrical Engineering Dec’07
San Jose State University, San Jose, CA
Relevant courses: Design of CMOS digital integrated circuits, Analog
Integrated circuits, High-speed CMOS circuits, Semi conductor devices and
Circuits, ASIC CMOS design, Large Scale MOS design
G.P.A: 3.5/4.0

Bachelor of Science degree in Electronics and Communication Engineering
Jawaharlal Nehru Technological University, India Apr ’05
Relevant courses: Pulse and Digital circuits, Switching theory and logic design,
Optical Communication, Radar Engineering, Digital communications, Linear and
Digital IC applications, Microprocessors and Microcontrollers, VLSI technology
G.P.A: 3.87/4.0

Skills:
Hardware : VHDL, Verilog,Veilog-AMS,
Cadence Virtuoso tools,
PSPICE,8085
Microprocessor, Ladder
logic for programming PLC’s
Synopsys DC compiler, RTL
Compiler,Prime Time, Model
Sim

Software :BASIC,C,Java

Operating
Systems : MS-DOS, Windows 2000/xp,
UNIX

Database : MS-Access
Scripting Lang’s : Perl

Additional Information:
ACADEMIC
PROJECTS
ASIC Module for Sorting:
• Designed a FIFO with random data to feed the module
• Used Binary Sort Technique to sort strings of varying length in ascending order
• Synthesized the design for 180 MHz operation
• Simulated and verified results in Model Sim for the test bench provided

Power Managed Hyper Transport system prototype for Transmission of
HD Video
• Designed a Power Managed hyper transport system prototype for transmission of HD(1080p) video in Verilog
• Design operates in sleep and active modes depending upon the video and the isochronous data flowing in the system, managing the power consumed
• Design was simulated using Model Sim and also was synthesized at 200 MHz using DC Compiler, timing reports were generated and verified.

4 bit A.L.U
• Designed a 4-bit ALU using cadence tools that performs 16 arithmetic/logical fns.
• Verified gate level schematic using NC verilog
• Implemented transistor level schematic and performed Layout
• Verified LVS extracted the circuit and performed static timing analysis

8 bit A.L.U using dynamic logic
• Designed a high speed 8-bit ALU using Domino Dynamic Logic
• Calculated sizes for transistors, implemented transistor level schematic
• Performed the Layout, Verified LVS
• Extracted the circuit and done static timing analysis

6 bit Digital to Analog Converter
• Designed a 6 bit DAC using TSMC 0.30u technology
• Calculated sizes for transistors, implemented transistor level schematic
• Designed a thermo decoder and current steering circuits
• Performed the Layout. Verified LVS
• Extracted the circuit and verified the functionality of the circuit

Programmable Logic Controller (PLC’s)
• Interfacing and Implementing a STEP 5 Programmable Logic controller for the
Automation of SBCNC machine
• PLC was programmed to control various tasks in a CNC machine which includes tool selection, the cutting dimensions , controlling the hydraulic motors etc
Organization: Bharat Heavy Electrical Limited (B.H.E.L), India

Candidate Contact Information:

Name: Adithya Kodati
Street:	Phone: 4088076489
City: San Jose	Fax: -
State: California
Zip: 95112
Web Site: